Integrated circuit (IC) devices typically contain a large number of active elements such as transistors forming a layer on a semiconductor die. The size and complexity of IC devices has increased over time, and the problems of efficient routing of signals from one element to another have increased accordingly.
Three-dimensional IC (3D-IC) devices have been proposed in which the active elements are arranged in more than one superimposed layer. 3D-IC devices are attractive because the third dimension allows greater freedom of design and can allow considerable reductions in signal path lengths. For certain applications, the more compact shape that can be achieved is desirable, and allows a robust device with a smaller, thinner, and lighter substrate than would be necessary for a comparable single-layer device.
Signals may be transferred from one layer to another layer in a 3D-IC by conductive vias extending through the layers. A via may consist of a hole through a silicon layer, lined with insulator and filled with metal. The 3D-IC device may then be fashioned by fabricating the layers separately, and stacking the layers so that exposed contacts on adjacent layers mate to establish electrical communication with the vias.
Forming vias passing vertically through the layers of silicon adds complexity to the fabrication process. The tolerances required for the etching process can limit the density of devices and other circuit components on the layers concerned. In addition, the electrical resistance of the vias, and their capacitive interaction with adjacent circuit components, can materially restrict the circuit design. In particular, RC time constants can restrict the speed of operation of circuits including such vias.